EPROM and Flash EPROM electronic memory devices integrated in a semiconductor include a number of non-volatile memory cells organized into a matrix; that is, the cells are arranged into rows, or word lines, and columns, or bit lines. Each non-volatile memory cell includes a MOS transistor with a floating gate electrode located above the channel region, i.e., shows a high d.c. impedance to all the other terminals of a cell and to the circuit in which the cell is incorporated.
The cell also includes a second electrode, known as the control gate, which is driven by suitable control voltages. The other electrodes of the transistor are conventional drain, source, and body terminals.
In recent years, considerable effort has been made to provide memory devices of higher circuit density. This has resulted in the development of electrically programmable non-volatile memory matrices of the contactless type, having a so-called "tablecloth" or crosspoint structure. One example of a matrix of this kind, and its fabrication process, is described in European Patent No. 0 573 728 to this Applicant, and is herein incorporated by reference.
In this class of matrices, the memory cells have source/drain regions formed in the substrate by continuous parallel diffusion strips, known as the bit lines, which are substantially coincident with the matrix columns.
A contactless matrix requires virtual ground circuitry for the reading and programming operations. However, the savings in circuit area afforded by such a structure is remarkable, allowing approximately of one order of magnitude higher number of contacts to be provided.
In this type of virtual ground matrix, parallel strips are defined of a which include a layer of gate oxide, a first layer of polysilicon, an interpoly dielectric layer, and a capping polysilicon layer known as the Poly Cap. These strips form the gate electrodes of the memory cells.
In openings between the various gate electrodes, an implantation, e.g., of arsenic where the substrate is of the P type, is performed to provide the source and drain region diffusion (bit lines).
At this stage of the process the gate electrodes, which are located between previously exposed bit lines, are sealed to permit the implanting steps. An oxidation step allows the dopant to diffuse under the gate electrodes.
This technique causes an increased resistance of the bit lines as the cell size decreases, particularly to less than 0.4-0.5 .mu.m. The resistance of implanted regions, such as the bit lines, is inversely proportional to the square of the width of those regions.
In addition, where the cell size is made exceedingly small, the length of the channel region becomes quite difficult to control. The actual length of the channel region of a MOS transistor is known to depend on: the size of the gate electrode, itself dependent on photolithography and etching operations on the polysilicon layers; implantations in the channel region controlling the cell performance in terms of threshold voltage and current; and the lateral diffusion of the implanted source/drain regions due by the thermal treatments to which the semiconductor is subjected after the implantation step.